Processes for forming moats or holes in electrically non-insulating substrates are well known in the art as exemplified in EP 0 296 348. There, adjacent moats or holes are formed in a silicon substrate by electrolytic etching. Such holes or moats in silicon are used in microelectronics and power electronics and thus, processes for forming such structures are becoming increasingly more important in silicon device fabrication. Moreover, recent trends in microelectronics and power electronics, have been to go to greater and greater device densities which necessitates finer device geometries and smaller separations. Accordingly, many chemical etching and plasma etching techniques have been developed and implemented for forming hole or moats patterns.
The disadvantage of such known processes is that the fine device geometries and small separations are difficult to form, especially for adjacently located moats or holes in close proximity to each other. The distance between the adjacently located moats or holes is limited by the photolithographic technique used to form the corresponding openings in the masking layer. More specifically, the minimum mask dimensions that are available for a specific lithographic process substantially determines the minimum size and separation of the moats or holes. With state-of-the-art technology it is problematic, for example, to form moats or holes in semiconductor substrates which are 5 .mu.s or less apart.
It is, therefore, the object of the present invention to provide an improved process for fabricating two closely spaced moats in an electrically non-insulating substrate.